This invention relates to integrated circuit semiconductor devices and more particularly to an improved memory device comprised of an array of single IGFET cells.
In the U.S. Pat. No. 4,003,036, which has the same assignee as this application, a semiconductor memory device having an array of cells is described wherein each cell is comprised of a buried storage capacitor located directly below a diffused line of opposite conductivity material from that of the substrate. A V-shaped recess formed in the surface of the device extends through the diffused line region into a buried storage capacitor region of the same conductivity. The walls of this recess form channel and gate areas interconnecting the line regions with the buried storage capacitor regions directly below. In a preferred embodiment, the diffused line regions served as bit lines and drain regions while transverse word lines were interconnected between the gates of adjacent cells. One disadvantage with the aforesaid structural arrangement was that a relatively large amount of gate-to-drain capacitance was created by the overlap of the gate regions on all walls of each recess with the diffused bit lines. This caused a relatively high overall bit line capacity which reduced the signal power capability of the buried storage capacitor for each cell. The present invention provides a solution to this problem.